1. Technical Field
Various embodiments of the present disclosure relate to an electro-static discharge (ESD) protection technology and, more particularly, to gate-coupled NMOS devices for ESD protection.
2. Related Art
Semiconductor devices generally include an ESD protection circuit between pads and inner circuits for protecting the inner circuits. A static electricity may be generated when the pad connected to an external pin of a microchip contacts a charged human body, a charged machine or a charge may be accumulated inside the circuit. The ESD protection circuit avoids chip fails due to the static electricity which is discharged into the inner circuit or flows into the inner circuit. In fabricating the microchips, a technique for designing a protection circuit from an ESD stress is one of key technologies of the chip design. A device used in designing a protection circuit for ESD stress is called an ESD protection device.
There are various types of ESD protection devices used to protect the microchip from ESD stress. A gate-grounded NMOS hereinafter referred to as a GGNMOS ESD protection device may be the most commonly used ESD protection device. The GGNMOS performs an ESD operation by turning-on a parasitic bipolar junction transistor by junction breakdown between a drain and a substrate.
However, a gate bias effect for the ESD protection operation of NMOS has been reported. According to the report, when a predetermined level of bias, for example, 1V to 2V, is applied to a gate of the NMOS, the NMOS can be triggered at a voltage lower than a voltage causing an avalanche breakdown. As such, to ensure that a predetermined level of bias is applied to the gate, a gate-coupled NMOS hereinafter referred to as GCNMOS, in which a capacitor is disposed between the gate and an input pad has been proposed.